Module

Filter Bank

The project opens two system diagrams and respective graphs.

License Requirements: VSS Time Domain (VSS_250+)

1. The Filter Bank system diagram shows a filter bank with 4 bandpass filters. The new RFSW_FRQ block is used to route the signals to the appropriate filter based on the signal frequency. Another RFSW_FRQ block is used after the filters to select the signal that corresponds to the appropriate filter and pass it to the output. The signal at the input of the filter bank is used to help the second RFSW_FRQ block identify the desired signal.
2. The Filter Bank Response graph displays the measured frequency response of each filter, and also the combined response of the filter bank.
3. A test bench is constructed to drive the filter bank with a modulated signal source, as shown in the "Modulated Test Bench" system diagram. The modulated signal frequency is switched and the output of the filter bank shows that it is tracking the signal frequency and selecting the appropriate filter internally.
4. Spectra of the input and output signals display on the "Modulated Signals" graph.

The project opens to two Schematic Views and their respective 2D Layout Views

License Requirements: Non-linear simulation and Layout (MWO_2X5+)

1. In "1Stage_Amp" notice the units are in microns.
2. In "Packaged_Amp" notice the units are in mils.
3. Observe that "1Stage_Amp" is instantiated as a subcircuit in the "Packaged_Amp" schematic.
   • Technologies are mixed, yet designers can operate in the preferred unit for that technology.
4. Open the AWR_MESFET layer process file.
   • Units can be set at an LPF level so designs using this technology operate in those units.
5. Open the "Gain vs Output Power" graph.
6. Right-click in the graph and choose Options to open the Rectangular Plot Options dialog box; click the Units tab.
   • Graphs can also honor technology so that performance metrics can be measured in the units of choice for a technology.
   • For example, MMIC designers may prefer GHz, while PCB/Module designers may prefer MHz.

The project opens to a Schematic Layout View, sets the appropriate layout mode options, and loads the appropriate DRC rules for the Minimum Space Routing guides.

License Requirements: Layout (MWO_105+)

1. Choose Layout > Layout Mode Properties to open the Layout Editor Mode Settings dialog box.
2. In the Routing options section, verify that Minimum spacing guides, Reject clicks inside min spacing, Constrain to outside min spacing, and Disable self avoidance guides are selected.
3. Choose Verify > Design Rule Check and look at the SEPARATION rules for each layer, then click Close.
4. In the Schematic Layout double-click the ratline and begin routing from the left area pin. Route the trace to end on the right area pin by following the minimum spacing guides.
   • Try changing routing layers as you are routing by pressing Ctrl + Shift while scrolling the mouse wheel.
   • Note the difference in separation distances between the trace versus the ground plane shapes.
5. Optionally, clear the check boxes you selected in step two. Leaving these options selected does not change behavior unless you have DRC rules loaded and are routing.

Reshape Route

The project will open to an iNet routed too close to a via.

1. Select the iNet.
2. Right-click on the iNet and choose Reshape Route.
3. Click on the lower half of the vertical segment to redraw that segment around the via (3 new segments).
4. Double-click on the route to finish.
5. Note: The old Redraw Route command is now called Extend Route.

Chamfered and rounded bend styles

The project will open to a Schematic Layout with an iNet spiral module inductor

1. Show the square bends of the iNet.
2. Right-click on the iNet and choose Shape Properties
3. Select the Route tab and change the Bend Style to Rounded.
4. View the 3D view of the layout to better see the bends.
5. Repeat the above steps but choose the Chamfered bend style.

Change iNet vias with hot key

The project will open to a Schematic Layout with an un-routed iNet (ratline)

1. Double-click on the ratline to start iNet routing.
2. Start routing an iNet, making sure to change Linetypes (CTRL + SHIFT + Mouse Wheel) so vias are automatically added.
3. Use Shift+V to change the via type of the last via created as you route.
4. Note the new via type becomes the default for that layer combination.

Move iNet vias

The project will open to a Schematic Layout with an iNet and vias in their default locations.

1. Double-click on a via.
2. Drag the via to a different location using the center drag handle.
3. You can also right-click on the via, choose Route Via Properties, un-check the box for Auto Size and enter in specific offset values.

Snap cell connections

The project will open to a Schematic Layout with several iNet routes connected to all six pins of an SMD footprint.

1. Begin dragging the footprint artwork cell, press Tab and enter 400 um for dx and click OK
2. Note you will have six new ratlines.
3. Rather than redraw all those routes, right-click on the artwork and choose Snap Cell Connections and all six iNets will automatically reconnect themselves to the pads.

Orthogonal start

The project will open to a Schematic Layout with an un-routed iNet (ratline) with one of the cells rotated 45 degrees.

1. Double-click on the ratline to begin a new iNet route.
2. Note you will have an inference guide and a gravity snap to allow you to easily maintain a route perpendicular to the face of the SMD pad.
3. Complete the route between the two SMDs.

Manage Multiple Technologies

This demo will show the improvements made to the framework to support multiple technologies in a single project.

1. Add a second built in example library (e.g. AWR PCB) through the Project > Process Library > Add/Remove Process Library dialog. Notice the improved list of available libraries.
2. Also, the Global Definitions document and the lpf were automatically added.
3. Create a new schematic. Notice how you can select the LPF. Choose one and create the schematic.
4. In the schematic options, notice how the LPF for the schematic and the Global Definitions document are set to match the process selected when creating the schematic.
5. Add a STACKUP to the schematic. Notice how the LPF for the schematic is set to match as well.

Cadence Spectre Co-simulation

The project will open to a Schematic and Graph window and simulate.

License requirements: Translated Spectre Designs (SPS-100), Nonlinear simulator (MWO-2XX), and VSS Communication standards (VSS-350)

1. The instance on the Schematic is an imported Spectre netlist.
2. Note the single tone Microwave Office results and the 802.11a 36 Mpbs VSS results
3. Imported designs are managed in PDKs so browse to Elements > Libraries > mmic_pkg > mmic_pkg and show that the translated design named mmic is available for placement.
4. Note that the symbol was imported from Cadence using the Open Access Import/Export Wizard and that the layout is an imported GDSII file.
5. If interested in the Spectre netlist import process choose Scripts > Demo > Import Spectre Netlist Demo and follow the script instructions.
6. Click Done to close the script.